Texas Instruments TMS320C6457 - Manual (Page 17)

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3.5 HHWIL: Identifying the First and Second Halfwords in 16-Bit Multiplexed Mode
In the 16-bit multiplexed mode, each host cycle consists of two consecutive halfword transfers. For each
transfer, the host must specify the cycle type with HCNTL[1:0] and HR/W, and the host must use HHWIL
to indicate whether the first or second halfword is being transferred. For HPID and HPIA accesses, HHWIL
must always be driven low for the first halfword transfer and high for the second halfword transfer. Results
are undefined if the sequence is broken. For examples of HHWIL usage, see the figures in
Section 3.6
and Section 3.7 .
When the host sends the two halfwords of a 32-bit word in this manner, the host can send the most and
least significant halfwords of the 32-bit word in either order (most significant halfword first or most
significant halfword second). However, the host must inform the HPI of the selected order before
beginning the host cycle. This is done by programming the halfword order (HWOB) bit of HPIC. Although
(HWOB) is written at bit 0 in HPIC, its current value is readable at both bit 0 and bit 8 (HWOBSTAT).
Thus, the host can determine the current halfword-order configuration by checking the least significant bit
of either half of HPIC.
There is one case when the 16-bit multiplexed mode does not require a dual-halfword cycle with HHWIL
low for the first halfword and HHWIL high for the second halfword. The least significant 16 bits of the HPIC
register can be accessed with a single-halfword cycle. During such a cycle, the host can drive HHWIL
either high or low. Either approach returns the same value.
Section 3.9 includes an example timing
diagram of this case.
In the 32-bit multiplexed mode, each host cycle is one word transfer. The HHWIL signal is ignored and 32
bits of data transferred for each active cycle of the internal strobe signal (internal HSTRB).
3.6 HAS: Forcing the HPI to Latch Control Information Early
The HAS signal is an address strobe that allows control information to be removed earlier in a host cycle,
allowing more time to switch bus states from address to data information. This feature facilitates the
interface for multiplexed address and data buses. In this type of system, an address latch enable (ALE)
signal is often provided and is normally the signal connected to HAS.
Figure 2 and Figure 4 show examples of signal connections when HAS is used for multiplexed transfers.
Figure 7 and Figure 8 show typical HPI signal activity when HAS is used. The process for using HAS is as
follows:
1. The host selects the access type. The host drives the appropriate levels on the HCNTL [1:0] and HR/W
signals, and indicates which halfword (first or second) will be transferred by driving HHWIL high or low.
2. The host drives HAS low. On the falling edge of HAS, the HPI latches the states of the HCNTL[1:0],
HR/W, and HHWIL. The high to low transition of HAS must precede the falling edge of the internal
strobe signal (internal HSTRB), which is derived from HCS, HDS1, and HDS2, as described in
Section 3.3 .
HCS does not gate the HAS input, which allows time for the host to perform the subsequent access. The
HAS signal may be brought high after internal HSTRB goes low, indicating that the data access is about to
occur. HAS is not required to be driven high at any time during the cycle, but eventually must transition
high before the host uses it for another access with different values for HCNTL [1:0], HR/W, and HHWIL.
17 SPRUGK7A – March 2009 – Revised July 2010 Host Port Interface (HPI)
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