Rainbow Electronics AT75C220 - Manual (Page 63)

AT75C220
63
PIO: Programmable I/O Controller
The AT75C220 integrates 24 programmable I/O pins (PIO).
Each pin can be programmed as an input or an output.
Each pin can also generate an interrupt. The programma-
ble I/O is implemented as two blocks, called PIO A and
PIO B, 14 and 10 pins each, respectively.
These pins are used for several functions:
• external I/O for internal peripherals
• keypad controller function
• general-purpose I/O
• visibility in test/debug mode, e.g., multiplex CBUS for the
Oak
The keypad controller is implemented by using up to ten
PIO B pins as row drivers and column sensors for an off-
chip switch matrix. This block is identical to the PIOA
except that only 14 pins are controlled.
The PIO B register map defines an set of registers identical
to the PIO A register map.
Every PIO B register allocates the same bit position to the
corresponding PIO B pin. These registers are otherwise
identical to the PIO A registers.
Multiplexed I/O Lines
Output Selection
The user can enable each individual I/O signal as an output
with the registers PIO_OER and PIO_ODR. The output sta-
tus of the I/O signals can be read in the register PIO_OSR.
The direction defined has an effect only if the pin is config-
ured to be controlled by the PIO controller.
I/O Levels
Each pin can be configured to be driven high or low. The
level is defined in four different ways, according to the fol-
lowing conditions:
If a pin is controlled by the PIO controller and is defined as
an output (see “Output Selection”), the level is programmed
using the registers PIO_SODR and PIO_CODR. In this
case, the programmed value can be read in the register
PIO_ODSR.
If a pin is controlled by the PIO controller and is not defined
as an output, the level is determined by the external circuit.
If a pin is not controlled by the PIO controller, the state of
the pin is defined by the peripheral (see peripheral
datasheets).
In all cases, the level on the pin can be read in the register
PIO_PDSR.
Interrupts
Each parallel I/O can be programmed to generate an inter-
rupt when a level change occurs. This is controlled by the
PIO_IER and PIO_IDR registers which enable/disable the
I/O interrupt by setting/clearing the corresponding bit in the
PIO_IMR. When a change in level occurs, the correspond-
ing bit in the PIO_ISR is set depending on whether the pin
is used as a PIO or a peripheral, and whether it is defined
as input or output. If the corresponding interrupt in
PIO_IMR is enabled, the PIO interrupt is asserted.
When PIO_ISR is read, the register is automatically
cleared.
User Interface
Each individual I/O is associated with a bit position in the
parallel I/O user interface registers. Each of these registers
is 32 bits wide. If a parallel I/O line is not defined, writing to
the corresponding bits has no effect. Undefined bits read
as zero.