Rainbow Electronics AT75C220 - Manual (Page 79)

AT75C220
79
Figure 20. Synchronous and Asynchronous Mode: Character Transmission
Break
A break condition is a low signal level which has a duration
of at least one character, including start/stop bits and par-
ity.
Transmit Break
The transmitter generates a break condition on the TXD
line when STTBRK is set in US_CR. In this case, the char-
acter present in the Transmit Shift Register is completed
before the line is held low.
To cancel a break condition on the TXD line, the STPBRK
command in US_CR must be set. The USART completes a
minimum break duration of one character length. The TXD
line then returns to high level (idle state) for at least 12 bit
periods to ensure that the end of break is correctly
detected. Then the transmitter resumes normal operation.
The break is managed like a character:
• The STTBRK and the STPBRK commands are
performed only if the transmitter is ready (bit TXRDY = 1
in US_CSR).
• The STTBRK command blocks the transmitter holding
register (bit TXRDY is cleared in US_CSR) until the
break has started.
• A break is started when the Shift Register is empty (any
previous character is fully transmitted).
US_CSR.TXEMPTY is cleared. The break blocks the
transmitter shift register until it is completed (high level
for at least 12 bit periods after the STPBRK command is
requested).
In order to avoid unpredictable states:
• STTBRK and STPBRK commands must not be
requested at the same time.
• Once an STTBRK command is requested, further
STTBRK commands are ignored until the break is ended
(high level for at least 12 bit periods).
• All STPBRK commands requested without a previous
STTBRK command are ignored.
• A byte written into the Transmit Holding Register while a
break is pending but not started (bit TXRDY = 0 in
US_CSR) is ignored.
• It is not permitted to write new data in the Transmit
Holding Register while a break is in progress (STPBRK
has not been requested), even though TXRDY = 1 in
US_CSR.
• A new STTBRK command must not be issued until an
existing break has ended (TXEMPTY = 1 in US_CSR).
The standard break transmission sequence is:
1. Wait for the transmitter ready
(US_CSR.TXRDY = 1).
2. Send the STTBRK command
(write 0x0200 to US_CR).
3. Wait for the transmitter ready
(bit TXRDY = 1 in US_CSR).
4. Send the STPBRK command
(write 0x0400 to US_CR).
The next byte can then be sent:
5. Wait for the transmitter ready
(bit TXRDY = 1 in US_CSR).
6. Send the next byte
(write byte to US_THR).
Each of these steps can be scheduled by using the inter-
rupt if the bit TXRDY in US_IMR is set.
For character transmission, the USART channel must be
enabled before sending a break.
Receive Break
The receiver detects a break condition when all data, parity
and stop bits are low. When the low stop bit is detected, the
receiver asserts the RXBRK bit in US_CSR. An end-of-
receive break is detected by a high level for at least 2/16 of
a bit period in asynchronous operating mode or at least one
sample in synchronous operating mode. RXBRK is also
asserted when an end-of-break is detected.
Both the beginning and the end of a break can be detected
by interrupt if the bit RXBRK in register US_IMR is set.
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit
Parity
Bit
Stop
Bit
Example: 8-bit, parity enabled 1 stop
Baud Rate
Clock