Rainbow Electronics AT75C220 - Manual (Page 122)

AT75C220
122
Master Mode
In master mode, the SPI controls data transfers to and from
the slave(s) connected to the SPI bus. The SPI drives the
chip select(s) to the slave(s) and the serial clock (SPCK).
After enabling the SPI, a data transfer begins when the
ARM core writes to the SP_TDR. For details on the SPI
memory map, refer to Table 27 on page 127.
Transmit and receive buffers maintain the data flow at a
constant rate with a reduced requirement for high-priority
interrupt servicing. When new data is available in the
SP_TDR, the SPI continues to transfer data. If the
SP_RDR has not been read before new data is received,
the Overrun Error (OVRES) flag is set.
The delay between the activation of the chip select and the
start of the data transfer (DLYBS) as well as the delay
between each data transfer (DLYBCT) can be programmed
for each of the four external chip selects. All data transfer
characteristics including the two timing values are pro-
grammed in registers SP_CSR0 to SP_CSR.
In master mode, the peripheral selection can be defined in
two different ways:
1. Fixed peripheral select: The SPI exchanges data
with only one peripheral.
2. Variable peripheral select: Data can be exchanged
with more than one peripheral.
Figure 28 and Figure 29 show the operation of the SPI in
master mode. For details concerning the flag and control
bits in these diagrams, see Table 27.
Fixed Peripheral Select
This mode is ideal for transferring memory blocks without
the extra overhead in the transmit data register to deter-
mine the peripheral.
Fixed peripheral select is activated by setting bit PS to zero
in SP_MR. The peripheral is defined by the PCS field, also
in SP_MR.
This option is only available when the SPI is programmed
in master mode.
Variable Peripheral Select
Variable peripheral select is activated by setting bit PS to
one. The PCS field in SP_TDR is used to select the desti-
nation peripheral. The data transfer characteristics are
changed when the selected peripheral changes according
to the associated chip select register.
The PCS field in the SP_MR has no effect.
This option is only available when the SPI is programmed
in master mode.
Chip Selects
The chip select lines are driven by the SPI only if it is pro-
grammed in master mode. These lines are used to select
the destination peripheral. The PCSDEC field in SP_MR
selects only one peripheral.
If variable peripheral select is active, the chip select signals
are defined for each transfer in the PCS field in SP_TDR.
Chip select signals can thus be defined independently for
each transfer.
If fixed peripheral select is active, chip select signals are
defined for all transfers by the field PCS in SP_MR. If a
transfer with a new peripheral is necessary, the software
must wait until the current transfer is completed, then
change the value of PCS in SP_MR before writing new
data in SP_TDR.
The value on the NPCS pins at the end of each transfer
can be read in the SP_RDR.
By default, all NPCS signals are high (equal to one) before
and after each transfer.
Mode Fault Detection
A mode fault is detected when the SPI is programmed in
master mode and a low level is driven by an external mas-
ter on the NPCS0/NSS signal.
When a mode fault is detected, the MODF bit in the SP_SR
is set until the SP_SR is read and the SPI is disabled until
re-enabled by bit SPIEN in the SP_CR.