Rainbow Electronics AT75C220 - Manual (Page 35)

AT75C220
35
Address Checking
Whether or not a frame is stored depends on what is
enabled in the network configuration register, the contents
of the specific address and hash registers and the frame's
destination address. In this implementation of the MAC the
frame’s source address is not checked.
A frame will not be copied to memory if the MAC is trans-
mitting in half-duplex mode at the time a destination
address is received.
The hash register is 64 bits long and takes up two locations
in the memory map.
There are four 48-bit specific address registers, each tak-
ing up two memory locations. The first location contains the
first four bytes of the address; the second location contains
the last two bytes of the address stored in its least signifi-
cant byte positions. The addresses stored can be specific,
group, local or universal.
Ethernet frames are transmitted a byte at a time, LSB first.
The first bit (i.e., the LSB of the first byte) of the destination
address is the group/individual bit and is set one for multi-
cast addresses and zero for unicast. This bit corresponds
to bit 24 of the first word of the specific address register.
The MSB of the first byte of the destination address corre-
sponds to bit 31 of the specific address register.
The specific address registers are compared to the desti-
nation address of received frames once they have been
activated. Addresses are deactivated at reset or when the
first byte [47:40] is written and activated or when the last
byte [7:0] is written. If a receive frame address matches an
active address, the local match signal is set and the store
frame pulse signal is sent to the DMA block via the HCLK
synchronization block.
A frame can also be copied if a unicast or multicast hash
match occurs, it has the broadcast address of all ones, or
the copy all frames bit in the network configuration register
is set.
The broadcast address of 0xFFFFFFFF is recognized if the
no broadcast bit in the network configuration register is
zero. This sets the broadcast match signal and triggers the
store frame signal.
The unicast hash enable and the multicast hash enable bits
in the network configuration register enable the reception of
Table 14. Received Buffer Descriptor List
Bit Function
Word 0
31:2 Address of beginning of buffer
1 Wrap bit. If this bit is set, the counter that is ORed with the received buffer queue pointer register to give the
pointer to entries in this table will be cleared after the buffer is used.
0 Ownership bit. 1 indicates software owns the pointer, 0 indicates that the DMA owns the buffer. If this bit is not
zero when the entry is read by the receiver, the buffer’s unavailable bit is set in the received status register and
the receiver goes inactive.
Word 1
31 Global all ones broadcast address detected
30 Multicast hash match
29 Unicast hash match
28 External address (optional)
27 Unknown source address (reserved for future use)
26 Local address match (Specific address 4 match)
25 Local address match (Specific address 3 match)
24 Local address match (Specific address 2 match)
23 Local address match (Specific address 1 match)
22:11 Reserved written to 0.
10:0 Length of frame including FCS