Rainbow Electronics AT75C220 - Manual (Page 8)

AT75C220
8
Architectural Overview
The AT75C220 integrates an embedded ARM7TDMI pro-
cessor. External SDRAM and SRAM/Flash interfaces are
provided so that processor code and data may be stored
off-chip.
The AT75C220 architecture consists of two main buses,
the Advanced System Bus (ASB) and the Advanced
Peripheral Bus (APB).
The ASB is designed for maximum performance. It inter-
faces the processor with the on-chip DSP subsystem and
the external memories and devices by the means of the
external bus interface (EBI).
The APB is designed for access to on-chip peripherals and
is optimized for low power consumption. The AMBA bridge
provides an interface between the ASB and APB.
The AT75C220 uses a multi-layer AMBA bus:
• It integrates two independent AMBA ASB buses. The two
buses are connected by a bridge that is not visible to the
other devices on the bus.
• The primary bus (ARM bus) is the main processor bus to
which most peripherals are connected.
• The secondary bus (MAC bus) is used exclusively for
Ethernet traffic.
The ARM7TDMI, USART DMA and ASB-ASB bridge
devices are masters on the ARM ASB bus, the MAC DMA
and ASB-ASB Bridge are masters on the MAC ASB bus
and the Flash/SRAM and SDRAM interfaces are ASB
slaves. For more details on bus arbitration, see “Arbitration
Using Multi-layer AMBA” on page 31.
All the peripherals are accessed by means of the APB bus.
An on-chip peripheral data controller (PDC) transfers data
between the on-chip USARTs and the memories without
processor intervention. Most importantly, the PDC removes
the processor input-handling overhead and significantly
reduces the number of clocks required for data transfer. It
can transfer up to 64K contiguous bytes without reprogram-
ming the starting address. As a result, the performance of
the microcontroller is increased and power consumption
reduced.
The AT75C220 peripherals are designed to be pro-
grammed with a minimum number of instructions. Each
peripheral has 16K bytes of address space allocated in the
upper part of the address space. The peripheral register set
is composed of control, mode, data, status and interrupt
registers.
To maximize the efficiency of bit manipulation, frequently-
written registers are mapped into three memory locations.
The first address is used to set the individual register bits,
the second resets the bit and the third address reads the
value stored in the register. A bit can be set or reset by writ-
ing a one to the corresponding position at the appropriate
address. Writing a zero has no effect. Individual bits can
thus be modified without having to use costly read-modify-
write and complex bit-manipulation instructions and without
having to store-disable-restore the interrupt state.
All of the external signals of the on-chip peripherals are
under the control of the parallel I/O controllers. The PIO
controllers can be programmed to insert an input filter on
each pin or generate an interrupt on a signal change. After
reset, the user must carefully program the PIO controllers
in order to define which peripherals are connected with off-
chip logic.
The ARM7TDMI processor operates in little-endian mode
in the AT75C220. The processor's internal architecture and
the ARM and Thumb instruction sets are described in the
ARM7TDMI datasheet, literature number 0673. The mem-
ory map and the on-chip peripherals are described in this
datasheet.
Peripheral Data Controller
The AT75C220 has a four-channel peripheral data control-
ler (PDC) dedicated to the two on-chip USARTs. One PDC
channel is connected to the receiving channel and one to
the transmitting channel of each USART.
The user interface of a PDC channel is integrated in the
memory space of each USART channel. It contains a 32-bit
address pointer register and a 16-bit count register. When
the programmed number of bytes is transferred, an end-of-
transfer interrupt is generated by the corresponding
USART. For more details on PDC operation and program-
ming, see the section describing the USART on page 74 .