Rainbow Electronics AT75C220 - Manual (Page 90)

AT75C220
90
USART Channel Status Register
Name: US_CSR
Access Type:Read-only
Reset Value: 0x18
• RXRDY: Receiver Ready
0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled.
1 = At least one complete character has been received and the US_RHR has not yet been read.
• TXRDY: Transmitter Ready
0 = US_THR contains a character waiting to be transferred to the Transmit Shift Register.
1 = US_THR is empty and there is no break request pending TSR availability.
Equal to zero when the USART is disabled or at reset. Transmitter enable command (in US_CR) sets this bit to one.
• RXBRK: Break Received/End of Break
0 = No break received or end of break detected since the last reset status bits command in the Control Register.
1 = Break received or end of break detected since the last reset status bits command in the Control Register.
• ENDRX: End-of-receive Transfer
0 = The end-of-transfer signal from the PDC channel dedicated to the receiver is inactive.
1 = The end-of-transfer signal from the PDC channel dedicated to the receiver is active.
• ENDTX: End-of-transmit Transfer
0 = The end-of-transfer signal from the PDC channel dedicated to the transmitter is inactive.
1 = The end-of-transfer signal from the PDC channel dedicated to the transmitter is active.
• OVRE: Overrun Error
0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the
last reset status bits command.
1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted
since the last reset status bits command.
• FRAME: Framing Error
0 = No stop bit has been detected low since the last reset status bits command.
1 = At least one stop bit has been detected low since the last reset status bits command.
• PARE: Parity Error
1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last reset status bit”
command.
0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since the last reset status bits
command.
• TIMEOUT: Receiver Time-out
0 = There has not been a time-out since the last start time-out command or the Time-out Register is 0.
1 = There has been a time-out since the last start time-out command.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – DMSI TXEMPTY TIMEOUT
7 6 5 4 3 2 1 0
PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY