Achronix Speedster22i Clock and Reset Networks - Manual (Page 14)

14 UG027, May 21, 2014
On the other hand, the “Advanced PLL” gives users much more flexibility in setting up the
individual PLL parameters, settings, counter values etc. and gives the user full control over
exactly how the PLL is tuned. Obviously, in the case of the “Advanced PLL”, it is the user’s
responsibility to ensure that the settings provided match the intended behavior.
PLL Cascading: An important feature with the PLLs in every corner of the device is the
ability to cascade them by feeding the output clock of one to the reference clock input of the
subsequent one. Each PLL can be cascaded with its neighbor only, in a circular fashion: PLL0
can generate the refclk for PLL1; PLL1 can generate the refclk for PLL2; PLL2 for PLL3; and
PLL3 for PLL0. Any of the four counter outputs can be used as a reference clock for the
neighboring PLL. However, in the rare cases where that is insufficient, a PLL output can also
be configured as bypass, so that the output follows refclk. So if PLL0 must provide the refclk
for both PLL1 and PLL2, you could use one output of PLL1 as bypass (leaving 3 outputs for
regular use), and drive PLL2 with that bypassed clock.
Refer to Figure 5 below for a graphical representation of this feature.
PLL0 PLL1 PLL2 PLL3
4 4 4
PLL reference clock PLL reference clock PLL reference clock PLL reference clock
PLL counter outputs PLL counter outputs PLL counter outputs PLL counter outputs
4
From clock
bank
From clock
bank
From clock
bank
From clock
bank
To clock network To clock network To clock network To clock network
Figure 5: PLL Reference Clock Cascading
The reference clock cascading mechanism is useful for a number of different reasons. Two of
the main ones are as follows:

It allows for a wider range of output phases/frequencies to be generated without
needing to use the fractional mode feature in PLLs.

It enables a larger set of clock outputs to be generated based off of the same reference
clock, without requiring changes at the board-level.
Clock Mux
There are two clock muxes in the FPGA, one at the top center of the device and one at the
bottom center. Each one of these is used to aggregate 128 clock signals coming in from all of
the clock sources described earlier (also shown below) and output a 32-bit bus that can be fed