Achronix Speedster22i Clock and Reset Networks - Manual (Page 27)

UG027, May 21, 2014 27
FPGA Core
Reset
source
Reset
source
Reset
source
Reset
source
8 bit
8 bit
8 bit
8 bit
8 bit
8 bit
8 bit
8 bit
P
Logic Block
P P P
P P
P
P P P
P P
P
P
P
P
P
P
P
P
P
P
P
P
Logic Block
Logic Block Logic Block
L
o
g
ic
B
lo
c
k
L
o
g
ic
B
lo
c
k
L
o
g
ic
B
lo
c
k
L
o
g
ic
B
lo
c
k
P
P
P
P
P
P
P
P
P P
P P P P
P P
Programmable
Pipeline
Figure 16: IO Ring Reset Network