Achronix Speedster22i Clock and Reset Networks - Manual (Page 28)

28 UG027, May 21, 2014
Revision History
The following table shows the revision history for this document.
Date Version Revisions
04/05/2013 1.0 Initial Achronix release.
05/22/2013 1.1 Incorporated additional inputs from engineering.
06/07/2013 1.2 Updated PLL description and diagrams.
04/24/2014 1.3
Updated byte-lane clocks. Added in boundary clock network
and settings sections. Corrected clock sources.
05/01/2014 1.4 Updated PLL specs.
05/21/2014 1.5 Added information about PLL cascading.