Achronix Speedster22i Clock and Reset Networks - Manual (Page 6)

6 UG027, May 21, 2014
Clock Sources
As mentioned earlier, the clock sources are Clock Generators (CGs) and recovered SerDes
input clocks.
There are four CGs on a Speedster 22iHD FPGA, one in each corner of the device. Each CG
contains six clock I/O buffers (CBs) and four Phase Locked Loops (PLLs). The clock buffers
can be used differential I/Os or single‐ended I/Os. If these I/Os are not used as clock buffers,
they can be used as generic inputs or outputs.
The PLLs are low jitter, wide range, independent multi-phase outputs with glitch-free phase
rotators that can be used for PLL outputs of up to 2 GHz for core circuit applications. The
PLLs support both integer mode and fractional mode operation.
Each pair of SerDes lanes is provided one reference clock. Each SerDes lane has its own pair
of PLLs listed below to generate and forward clocks to the fabric:
a. A transmit PLL, which synthesizes the Tx clock directly from the reference clock,
and then a slower Tx word-clock for data-input from the fabric,
b. A receive PLL, which synthesizes a Rx bit-clock (and corresponding word-clock)
from the incoming data-stream.
Thus each SerDes lane provides two word-clocks (Tx and Rx) to the fabric.
For source synchronous transfers, there are additional clock networks known as byte-lane
clock networks that may be used especially when a small amount of logic in the fabric needs
clocking. In these cases, clocks can be routed directly into the fabric along with the data.
Reset Sources
Each corner of a Speedster22i FPGA has an individual Reset Input Block. This block receives
external reset inputs as well as inputs generated internally within the device. External reset
inputs can be driven by dedicated clock pads as well as a number of GPIOs located in the
East-North (EN), East- South (ES), West-North (WN) or West-South (WS) sides of the device.
Internal reset inputs are driven through data and clock paths in the logic fabric.
The inputs to the Reset Input Block generated either externally or internally are required to
be active‐low and glitch free. The input resets can be either asynchronous or synchronous. An
asynchronous reset is synchronized for de‐assertion to each and every clock domain where it
is utilized. A synchronous reset does not need to be synchronized to the same clock domain
but is synchronized when used in any other clock domain not synchronous with the current
clock domain.