Achronix Speedster22i Clock and Reset Networks - Manual (Page 24)

24 UG027, May 21, 2014
Reset Network
This chapter examines the reset network in a little more detail and provides information on
the different networks, reset sources as well as associated circuitry in Speedster22i FPGAs.
Reset Sources and the Reset Input Block
Each corner of a Speedster22i FPGA has an individual Reset Input Block. This block receives
external reset inputs as well as inputs generated internally within the device. External reset
inputs can be driven by dedicated clock pads as well as a number of GPIOs located in the
East-North (EN), East- South (ES), West-North (WN) or West-South (WS) sides of the device.
Internal reset inputs are driven through data and clock paths in the logic fabric. Figure 14
below illustrates a Reset Input Block in the bottom-left corner of the device and the
appropriate signals coming in to the block.
Reset
Input
Block PLL
GCGs
PLL PLLs Clock
Buffers
I/O
Bank
B
y
te
L
a
n
e
s
B
y
te
L
a
n
e
s
FPGA Core
Figure 14: Reset Input Block
The inputs to the Reset Input Block generated either externally or internally are required to
be active‐low and glitch free. The input resets can be either asynchronous or synchronous.
For resets to IO ring resources, there is automatic reset synchronization (using boundary
clocks) and pipelining to ensure that while reset assertion is asynchronous, the deassertion is
synchronous. The purpose of the reset pipeline insertion is to ensure that reset deassertion in
the I/O ring meets setup and hold time requirements, and occurs at the same clock tick for all
targets. This is done because (a) the STA does not verify timing requirements in the I/O ring,