Achronix Speedster22i Clock and Reset Networks - Manual (Page 8)

8 UG027, May 21, 2014
GPIO GPIO
SerDes
SerDes
GCG
GCG
GCG
GCG
Figure 1: Global Core Clock Network
Direct Core Clock Network
The direct core clock network is a distribution system that provides for much lower clock
insertion delay, which is particularly useful for more complex designs that utilize multiple
clocks and require clocks to be internally generated and re-distributed to certain parts of the
FPGA fabric. Each branch of the direct clock network is restricted to the clock region it
reaches. Furthermore, direct clocks in each of the clock regions have different insertion
delays, which may result in significant inter-region clock skew.
The clock sources for the direct core clock network are fundamentally the same as those for
the global core clock network. The main difference between the direct and global clocks is
that direct clocks get distributed to the clock regions directly out of the top and bottom clock
muxes, without going through the clock hub (H-tree) in the center of the device.
There are a total of 32 direct clocks coming in from the top clock mux, and 32 coming in from
the bottom clock mux. A pre-designated set of 12 clocks from this group of 32 is distributed
to every clock region. Once inside the clock region, these 12 clocks are then muxed with other
incoming clocks to provide for the set of 16 that ultimately goes into the LUTs, memories and
DSPs in that clock region.
Figure 2 below illustrates the direct core clock network hierarchy.