ADLINK DAQe-2502 - Manual (Page 52)

42 Operation Theory
When IC_counter is disabled, the waveform generation does not
stop until a stop trigger is asserted. For Stop Mode, refer to the
next section.
An onboard data FIFO is used to buffer the waveform patterns for
waveform generation. If the size of a single waveform is smaller
than that of the FIFO, after initially loading the data from the host
memory, the data in FIFO is re-used when a single waveform gen-
eration is completed. It does not occupy the PCI bandwidth after-
wards. However, if the size of a single waveform is larger than that
of the FIFO, it needs to be intermittently loaded from the host
memory via DMA, thus occupying the PCI bandwidth.
If the value specified in UC_counter is smaller than the sample
size of the waveform patterns, the waveform is generated piece-
wisely. For example, if you defined a 16-sample sine wave and set
the UC_counter to two, the generated waveform will be a 1/8-cycle
sine wave for every waveform period. A complete sine wave will
be generated for every 8-iterations. If value specified in the
UC_counter is larger than the sample size of waveform LUT, i.e.
32, the generated waveform will be a 2-cycle sine wave for every
waveform period.
In conjunction with different trigger modes and counter setups, you
can manipulate a single waveform to generate different, more
complex waveforms. For more information, refer to the Appendix.
DLY2_Counter in iterative Waveform Generation
To expand the flexibility of Iterative Waveform Generation,
DLY2_counter was implemented to separate consecutive
waveform generations.
The DLY2_counter starts counting down immediately after a
single waveform generation is completed. When it reaches
zero, the next iteration of waveform generation starts. If you are
generating waveform piece-wisely, the next piece of wave-
form is generated. The DLY2_counter clock source can be
software selected from internal 40 MHz timebase, external
clock input (AFI-0), or GPTC output 0/1.