Bus-mastering dma data transfer – ADLINK DAQe-2502 User Manual
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Operation Theory
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Bus-mastering DMA Data Transfer
Bus Mastering DMA Mode
PCI bus-mastering DMA is necessary for high speed DAQ in
order to utilize the maximum PCI bandwidth. The bus-master-
ing controller, which is built in the PLX PCI controller, controls
the PCI bus when it becomes the master of the bus. Bus mas-
tering reduces the required size of the onboard memory and
reduces the CPU loading because data is directly transferred
to the computer’s memory without host CPU intervention.
The hardware temporarily stores the acquired data in the
onboard Data FIFO buffer, then transfers the data to the user-
defined DMA buffer in the host PC’s memory. Bus-mastering
DMA utilizes the fastest available transfer rate of PCI-bus.
Once the analog acquisition operation starts, control returns to
your program.
DMA with Scatter Gathering Capability
In multi-user or multi-tasking OS such as Microsoft Windows,
Linux, etc., it is difficult to allocate a large continuous memory
block to do the DMA transfer due to memory fragmentation.
PLX PCI controller provides scatter/gather or chaining mode to
link non-continuous memory blocks into a linked list, so you
can transfer large amounts of data without being limited by the
fragment of memory blocks. You can configure the linked list
for the input DMA channel and the output DMA channel, indi-
vidually.
Figure 4-5 shows a linked list that is constructed by three DMA
descriptors. Each descriptor contains a PCI address, a local
address, a transfer size, and the pointer to the next descriptor.
You can collect fragmented memory blocks and chain their
associative DMA descriptors altogether. The DAQ-/DAQe-/
PXI-2502/2501 software driver simple settings for the scatter/