ADLINK DAQe-2502 - Manual (Page 56)

46 Operation Theory
4.4 General Purpose Timer/Counter Operation
Two independent 16-bit up/down timer/counter are embedded in
FPGA firmware for user applications. They have the following fea-
tures:
X
Counting direction can be controlled via hardware or soft-
ware
X
Selectable counter clock source from either internal or
external clock up to 10 MHz
X Programmable gate selection
X Programmable input and output signal polarities, either
active-high or active-low
X
Initial Count can be loaded via software
X
Current count value can be read-back by software without
affecting circuit operation
Basics Timer/Counter Function Basics
Each timer/counter has three inputs that can be controlled via
hardware or software. These are clock input (GPTC_CLK), gate
input (GPTC_GATE), and up/down control input
(GPTC_UPDOWN).
The GPTC_CLK input acts as a clock source to the timer/counter.
Active edges on the GPTC_CLK input increment or decrement the
counter. The GPTC_UPDOWN input determines whether the
counter is counting up or down. The GPTC_GATE input is a con-
trol line that acts as a counter enable or a counter trigger signal in
different modes.
The output of timer/counter is GPTC_OUT. After power-up,
GPTC_OUT is pulled high by a 10K resistor. GPTC_OUT goes
low after the DAQ board is initialized.
All the polarities of input/output signals can be programmed via
software. In this section, all timing figures assume that
GPTC_CLK, GPTC_GATE, and GPTC_OUT are set to be posi-
tive-logic, meaning they’re triggered on the rising-edge.