Altera Device-Specific Power Delivery Network - Manual (Page 27)

The power regulators must be able to supply the total combined current requirements for each load on the
supply, but the decoupling capacitor selections should be analyzed on a single FPGA basis.
Troubleshooting Z
EFF
When the decoupling mode is set to Auto, this may result in a Z
EFF
value that is too high. This can
happen when the PCB parameters you entered result in an inefficient PDN, and the current to be
decoupled by the PCB are unrealistically high.
With difficult PCB and current parameters, auto decoupling continues to add decoupling capacitors until
it determines they have little effect. This results in hundreds of capacitors. You can achieve decoupling
schemes with similar performance manually using far fewer capacitors.
Strategies for Correcting a High Z
EFF
As well as decoupling manually, you can reduce the decoupling burden by accurately estimating your
current requirements and making your PCB more efficient. You may be able to achieve reduced PCB
current requirements in the following ways:
• Estimating realistic current requirements in the Altera Early Power Estimator (EPE).
• Entering realistic toggle rate figures for the logic in the EPE. Unrealistic, high toggle rates dramatically
increases dynamic current requirements.
• Entering realistic logic requirements in the EPE.
• Entering realistic clock frequencies in the EPE.
• Using the Quartus II software (Power Play Power Analyzer) PPPA and .vcd simulation entry for
accurate current requirement estimation.
• Considering Root Sum Squared (RSS) averaging for shared power supply rails. Refer to the Introduc‐
tion tab of the PDN tool for more information on this method.
You can make the PCB more efficient in the following ways:
• Increasing inter-plane capacitance of your Power (PWR) and Ground (GND) plane pair by reducing
their dielectric thickness.
• Increasing inter-plane capacitance of your PWR and GND plane pair by increasing their surface area.
• Reducing loop inductance from the PWR and GND plane pair to the FPGA. You can do this by
moving them closer to the surface of the PCB where the FPGA is mounted.
• Reducing loop inductance from the high frequency decoupling capacitors to the PWR and GND plane
pair. You can do this by placing them on the surface of the PCB that is closest to the planes.
• Using Via On Side (VOS) instead of Via On End (VOE) capacitor mounting topologies to help at high
frequencies.
• Using ultra-low Effective Series Inductance (ESL) mounting capacitors to help at high frequencies, for
example, X2Y package style.
• Using ultra-low Effective Series Resistance (ESR) bulk capacitors to help at low frequencies.
• Considering larger vias with less ESL.
UG-01157
2015.03.06
Troubleshooting Z
EFF
27
Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide Altera Corporation
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