Altera Device-Specific Power Delivery Network - Manual (Page 3)

For first order analysis, the VRM can be simply modeled as a series-connected resistor and inductor as
shown above. The VRM has a very low impedence and can respond to the instantaneous current require‐
ments of the FPGA in the following circumstances:
• At low frequencies up to approximately 50 KHz
• Depending on the voltage regulation module you use
The equivalent series resistance (ESR) and equivalent series inductance (ESL) values can be obtained from
the VRM manufacturer. At higher frequency, the VRM impedance is primarily inductive, making it
incapable of meeting the transient current requirement.
PCB decoupling capacitors are used for reducing the PDN impedance up to 100-150 MHz. The on-board
discrete decoupling capacitors provide the required low impedance. This depends on the capacitor-
intrinsic parasitics (R
cN
, C
cN
, L
cN
) and the capacitor mounting inductance (L
mntN
). The inter-planar
capacitance between the power-ground planes typically has lower inductance than the discrete decoupling
capacitor network, making it more effective at higher frequencies up to 150 MHz. As frequency increases,
the PCB decoupling capacitors become less effective. The limitation comes from the parasitic inductance
seen with respect to the FPGA. FPGA parasitic inductance includes capacitor mounting inductance, PCB
spreading inductance, ball grid array (BGA) via inductance, and packaging parasitic inductance. All of
these parasitics are modeled in the PDN tool 2.0 to capture the effect of the PCB decoupling capacitors
accurately. To simplify the circuit topology, all parasitics are represented with lumped inductors and
resistors despite the distributed nature of PCB spreading inductance.
Z
TARGET
According to Ohm’s law, voltage drop across a circuit is proportional to the current flow through the
circuit, and impedance of the circuit. The dynamic component of PDN current gives rise to voltage
fluctuation within the PDN, which may lead to logic and timing issues. You can reduce excessive voltage
fluctuation by reducing PDN impedance. One design guideline is target impedance, Z
TARGET
. Z
TARGET
is
defined using the maximum allowable die noise tolerance and dynamic current change, and is calculated
as follows.
Figure 2: Z
TARGET
Equation
Z
TARGET
=
Voltage Rail ×
100
Die Noise Tolerance%
( )
Maximum Dynamic Current Change
For example, to reliably decouple a 1.8-volt power rail that allows 5% of die noise tolerance and a
maximum 2 A current draw, 50% of which is dynamically changing, the desired target impedance is
calculated as follows.
Figure 3: Z
TARGET
Example Equation
Z
TARGET
=
2 × 0.5
0.09 Ω =
1.8 × 0.05
UG-01157
2015.03.06
Z
TARGET
3
Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide Altera Corporation
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