Altera Arria II GX FPGA - Manual (Page 34)

6–14 Chapter 6: Board Test System
Using the Board Test System
Arria II GX FPGA Development Kit User Guide February 2011 Altera Corporation
The following sections describe the controls on the DDR2 tab.
Start
This control initiates DDR2 memory transaction performance analysis.
Stop
This control terminates transaction performance analysis.
Performance Indicators
These controls display current transaction performance analysis information collected
since you last clicked Start:
■ Write , Read, and Total performance bars—Show the percentage of maximum
theoretical data rate that the requested transactions are able to achieve.
■ Write (MBytes/s) , Read (MBytes/s), and Total (MBytes/s)—Show the number of
bytes of data analyzed per second. The data bus is 64 bits wide and the frequency 1
is 333 MHz double data rate (667 Mbps per pin), equating to a theoretical
maximum bandwidth of 5333 MBps.
Error Control
This control displays data errors detected during analysis and allows you to insert
errors:
■ Detected Errors —Displays the number of data errors detected in the hardware.
■ Inserted Errors —Displays the number of errors inserted into the transaction
stream.
■ Insert Error —Inserts a one-word error into the transaction stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
■ Clear —Resets the Detected errors and Inserted errors counters to zeros.
Number of Addresses to Write/Read
This control determines the number of addresses to use in each iteration of reads and
writes. Valid values range from 8 to 134217728.
■ The minimum range, when on the slider is at the Min position on the left, is the
maximum PHY burst of 8.
■ The maximum range, when the slider is at the Max position on the right, fills the
full address space of the DDR2 SODIMM.
Data Type
This control specifies the type of data contained in the transactions. The following
data types are available for analysis:
■ PRBS —Selects pseudo-random bit sequences.
1 Frequency rates for production silicon speed grade C4N only.