Altera Arria II GX FPGA - Manual (Page 43)

Appendix A A–3
Programming Flash Memory Using the Board Update Portal
February 2011 Altera Corporation Arria II GX FPGA Development Kit User Guide
2. In the Nios II command shell, navigate to the directory where your design files
reside and type the following Nios II EDS commands:
■ For Quartus II .sof files:
sof2flash --input=<yourfile>_hw.sof --output=<yourfile>_hw.flash --offset=0x00640000 --
pfl --optionbit=0x18000 --programmingmode=PS
r
■ For Nios II .elf files:
elf2flash --base=0x08000000 --end=0x0BFFFFFF --reset=0x0A020000
--input=<yourfile>_sw.elf --output=<yourfile>_sw.flash
--boot=$SOPC_KIT_NIOS2/components/altera_nios2/boot_loader_cfi.srec
r
1
For boards with dual-die CFI flash devices, use --base=0x0A000000. For
more information, refer to the Board Revision History appendix of the
Arria II GX FPGA Development Board Reference Manual .
The resulting .flash files are ready for flash device programming. If your design uses
additional files such as image data or files used by the runtime program, you must
first convert the files to .flash format and concatenate them into one .flash file before
using the Board Update Portal to upload them.
1
The Board Update Portal standard .flash format conventionally uses either
<filename>_hw.flash for hardware design files or <filename>_sw.flash for software
design files.
Programming Flash Memory Using the Board Update Portal
Once you have the necessary .flash files, you can use the Board Update Portal to
reprogram the flash memory. Refer to
“Using the Board Update Portal to Update User
Designs” on page 5–2 for more information.
1 If you have generated a .sof that operates without a software design file, you can still
use the Board Update Portal to upload your design. In this case, leave the Software
File Name
field blank.
Programming Flash Memory Using the Nios II EDS
The Nios II EDS offers a nios2-flash-programmer utility to program the flash memory
directly. To program the .flash files or any compatible S-Record File (.srec) to the
board using nios2-flash-programmer, perform the following steps:
1. Set the USER_LOAD switch (SW4.4) to the off position to load the Board Update
Portal design from flash memory on power up.
2. Attach the USB-Blaster cable and power up the board.
3. If the board has powered up and the LCD displays either "Connecting..." or a valid
IP address (such as 152.198.231.75), proceed to step 8 . If no output appears on the
LCD or if the CONF DONE LED (D14) does not illuminate, continue to step 4 to
load the FPGA with a flash-writing design.
4. Launch the Quartus II Programmer to configure the FPGA with a .sof capable of
flash programming. Refer to “Configuring the FPGA Using the Quartus II
Programmer” on page 6–20 for more information.