Altera Clock Control Block IP Core - Manual (Page 10)

2–4 Chapter 2: Parameter Settings
MegaWizard Parameter Settings
Clock Control Block (ALTCLKCTRL) Megafunction February 2014 Altera Corporation
User Guide
6 Summary Page
Specify the types of files to be generated. Only the files
marked with red check marks are optional.
Choose from the following types of files:
■ Variation file (4)
■ AHDL Include file (<function name>.inc)
■ VHDL component declaration file
(<function name>.cmp)
■ Quartus II symbol file (<function name>.bsf)
■ Instantiation template file (<function name>_inst.v)
■ Verilog HDL black box file (<function name>_bb.v)
■ Synthesis area and timing estimation netlist
(_syn.v)
(5)
For more information about the wizard-generated files,
refer to Quartus II Help or to the
Recommended HDL
Coding Styles chapter in volume 1 of the Quartus II
Handbook.
Notes to Table 2–1 :
(1) This option is not supported in Cyclone III devices.
(2) You can change the number of clock inputs only if you choose the Auto or For global clock options.
(3) Not supported if you choose the For periphery clock option.
(4) The Variation file contains wrapper code in the language you specified on page 2a and is automatically generated.
(5) The synthesis area and timing estimation netlist file (_syn.v) is automatically generated if the Generate netlist option on page 4 is turned on.
(6) This mode is not supported in Arria 10 devices.
Table 2–1. ALTCLKCTRL MegaWizard Plug-In Manager Page Options and Description (Part 4 of 4)
MegaWizard
Plug-in
Manager
Page
Configuration Setting Description