Altera Clock Control Block IP Core - Manual (Page 15)

Chapter 3: Functional Description 3–3
Clock Control Block
February 2014 Altera Corporation Clock Control Block (ALTCLKCTRL) Megafunction
User Guide
Regional Clock Control Block
When the clock control block is configured to drive a regional clock network, you can
only control the clock source selection statically. You can set any inputs to the clock
select multiplexer as the clock source.
Figure 3–2 shows a clock control block configured to drive a regional clock network.
The unused global and regional clock networks are powered down automatically in
the configuration file generated by the Quartus II software. The dynamic clock enable
feature allows the internal logic to control the power for the GCLK and RCLK
networks. You can enable or disable the clock network with the ALTCLKCTRL
megafunction.
f For more information about regional clock control block or network in a specific
device, refer to the respective device handbook.
External PLL Output Clock Control Block
When the clock control block is configured to drive the dedicated external clock out,
you can only control the clock source selection statically. You can only set the PLL
outputs as the clock source.
Figure 3–2. Regional Clock Control Block
Notes to Figure 3–2 :
(1) You can only control these clock select signals through a configuration file and cannot be dynamically controlled
during user-mode operation.
(2) Only the CLKn pins on the top and bottom of the device feed to the regional clock control blocks.
RCLK
Internal Logic
Enable/
Disable
2
PLL Counter Outputs Internal Logic
Static Clock Select
(1)
CLK p Pin CLK n Pin
(2)