Altera Clock Control Block IP Core - Manual (Page 21)

Chapter 3: Functional Description 3–9
Prototypes and Component Declarations
February 2014 Altera Corporation Clock Control Block (ALTCLKCTRL) Megafunction
User Guide
clkselect:in std_logic_vector(width_clkselect-1 downto 0) :=
(others => '0');
ena : in std_logic := '1';
inclk: in std_logic_vector(number_of_clocks-1 downto 0) :=
(others => '0');
outclk:out std_logic
);
end component;
VHDL LIBRARY-USE Declaration
The VHDL LIBRARY-USE declaration is not required if you use the VHDL
component declaration.
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;