Altera Clock Control Block IP Core - Manual (Page 23)

February 2014 Altera Corporation Clock Control Block (ALTCLKCTRL) Megafunction
User Guide
Additional Information
This chapter provides additional information about the document and Altera.
Document Revision History
The following table lists the revision history for this document.
Date Version Changes
February 2014 3.1
■ Updated the “ALTCLKCTRL Megafunction Parameters” on page 2–5 to add the
information for the How do you want to register the 'ena' port? and How do you want to
use the ALTCLKCTRL? parameter settings.
■ Updated Table 3–1 on page 3–1 to include Arria 10 and Stratix V devices information.
Also added a row for Large Periphery Clocks.
■ Added “Double Register Clock Enable Circuit” on page 3–5 .
■ Removed “Stratix II Devices Restrictions”, “Design Example: Global Clock Buffer”, and
“Functional Simulation in the ModelSim-Altera Software” because beginning from
Quartus II software version 13.1, Stratix II devices are no longer supported.
February 2012 3.0
■ Updated information for switchover usage.
■ Added a note about assigning clock type through assignment editor.
September 2010 2.5 Updated ports and parameters