Altera Clock Control Block IP Core User Manual
Page 8
2–2
Chapter 2: Parameter Settings
MegaWizard Parameter Settings
Clock Control Block (ALTCLKCTRL) Megafunction
February 2014
Altera Corporation
User Guide
How do you want to use the ALTCLKCTRL?
Specify the ALTCLKCTRL buffering mode. You can select
from the following modes:
—Allows the Compiler to pick the best clock
buffer to use.
For global clock—Allows a clock signal to reach all parts
of the chip with the same amount of skew; you can select
input port clkselect to switch between the four clock
inputs.
For dual regional clock—half chip
,
—Allows a
clock signal to reach half of the chip by using two
regional clocks to drive two quadrants; only one clock
input is accepted.
For regional clock —quarter chip
—Allows a clock
signal to reach a quadrant of the chip; only one clock
input is accepted.
For regional clock—This mode is available for Arria 10
devices only. Allows a clock to reach a region covering
six interface tiles vertically (two at the edge of the
device), and the entire chip horizontally.
For external path
—Represents the clock path from
the outputs of the PLL to the dedicated clock output pins;
only one clock output is accepted.
For periphery clock
—Allows a clock signal to reach a
quadrant or an octant of the chip depending on the
device; only one clock input is accepted. For tile-based
architectures like Arria 10 devices, a periphery clock will
reach a region aligned with the source interface tile, and
half the chip horizontally.
How many clock inputs would you like?
Specify the number of input clock sources for the clock
control block. You can specify up to four clock inputs.
Create ‘ena’ port to enable or disable the clock
network driven by this buffer
Turn on this option if you want to create an active high
clock enable signal to enable or disable the clock
network.
Table 2–1. ALTCLKCTRL MegaWizard Plug-In Manager Page Options and Description (Part 2 of 4)
MegaWizard
Plug-in
Manager
Page
Configuration Setting
Description