Development board setup, Introduction, Setting up the board – Altera Cyclone III LS FPGA User Manual
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© October 2009 Altera Corporation
Cyclone III LS FPGA Development Kit User Guide
4. Development Board Setup
Introduction
The instructions in this chapter explain how to set up the Cyclone III LS FPGA
development board.
Setting Up the Board
To set up and power up the board, perform the following steps:
1. The Cyclone III LS FPGA development board ships with its board switches
preconfigured to support the example designs in the development kit. If you
suspect your board might not be currently configured with the default settings,
follow the instructions in
“Factory Default Switch Settings” on page 4–2
to return
the board to its factory settings before proceeding.
2. The development board ships with example designs stored in the flash memory
device. Verify the PGM/USER LOAD switch (SW2.6) is set to the on position to
load the design stored in the factory portion of flash memory.
shows the
switch location on the Cyclone III LS FPGA development board.
3. Connect the DC adapter (+16 V, 3.75 A) to the DC power jack (J5) on the FPGA
board and plug the cord into a power outlet.
c
Use only the supplied power supply. Power regulation circuitry on the
board can be damaged by power supplies with greater voltage.
4. Set the POWER switch (SW1) to the on position. When power is supplied to the
board, a blue LED (D3) illuminates indicating that the board has power.
The MAX II device on the board contains a parallel flash loader (PFL) megafunction.
When the board powers up, the PFL reads one of two designs from flash memory and
configures the FPGA. The PGM/USER LOAD switch (SW2.6) controls which design
to load. When the switch is in the on position, the PFL loads the design from the
factory portion of flash memory. When the switch is in the off position, the PFL loads
the design from the user portion of flash memory.
1
The development kit includes the MAX II configuration design in the <install
dir>\kits\cycloneIIILS_3cls200_fpga\examples\max2 directory.
When configuration is complete, the CONF DONE LED (D14) illuminates, signaling
that the Cyclone III LS device configured successfully. If the loaded design has the
Quartus II software INIT_DONE option on, the FPGA INIT DONE LED (D14)
illuminates when the device enters user mode.
f
For more information about the PFL megafunction, refer to