Altera Cyclone III LS FPGA - Manual (Page 39)

Appendix A: Programming the Flash Memory Device A–5
Restoring the MAX II CPLD to the Factory Settings
© October 2009 Altera Corporation Cyclone III LS FPGA Development Kit User Guide
12. Cycle the POWER switch (SW1) off then on to load and run the restored factory
design.
13. The restore script cannot restore the board’s MAC address automatically. In the
Nios II command shell, type the following Nios II EDS command:
nios2-terminal
r
and follow the instructions in the terminal window to generate a unique MAC
address.
f To ensure that you have the most up-to-date factory restore files and information
about this product, refer to the
Altera Development Kits page on the Altera website.
Restoring the MAX II CPLD to the Factory Settings
This section describes how to restore the original factory contents to the MAX II CPLD
on the development board. Make sure you have the Nios II EDS installed, and
perform the following instructions:
1. Set the board switches to the factory default settings described in “Factory Default
Switch Settings” on page 4–2 .
1
Installing the shunt jumper on jumper J11 pins 1-2 includes the MAX II
device in the JTAG chain. Installing the shunt jumper on jumper J12 or
setting DIP switch SW2.3 to the off position breaks the JTAG chain.
2. Launch the Quartus II Programmer.
3. Click Auto Detect.
4. Click Add File and select <install
dir>\kits\cycloneIIILS_3cls200_fpga\factory_recovery\max2.pof.
5. Turn on the Program/Configure option for the added file.
6. Click Start to download the selected configuration file to the MAX II CPLD.
Configuration is complete when the progress bar reaches 100%.
f To ensure that you have the most up-to-date factory restore files and information
about this product, refer to the
Cyclone III LS FPGA Development Kit page on the
Altera website.