Altera Cyclone III LS FPGA - Manual (Page 30)

6–12 Chapter 6: Board Test System
Using the Board Test System
Cyclone III LS FPGA Development Kit User Guide © October 2009 Altera Corporation
1
You must have the loopback HSMC installed on the HSMC connector that you are
testing for this test to succeed.
The following sections describe the controls on the HSMC tab.
Status
This control displays the following status information during the loopback test:
 PLL Lock —Shows the PLL locked or unlocked state.
 Channel Lock —Shows the channel locked or unlocked state. When locked, all
lanes are aligned and bonded.
 Pattern Sync —Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
Port
This control allows you to specify the type of test to run on the HSMC ports. The
following HSMC port tests are available:
Figure 6–6. The HSMC Tab