Altera First-In-First-Out Partitioner - Manual (Page 14)

12 Altera Corporation
FIFO Partitioner Megafunction User Guide Getting Started
FIFO Write-port Functionality
Each FIFO write-port includes an independent set of control and data
signals. The clk_port_a_n input is used to clock the write operations
for FIFO n. The wr_full_n must not be asserted during a write
operation. If wr_full_n is asserted, wait for it to deassert before
performing a write operation. To write to the FIFO, put the data to be
written on write_data_a_n, and assert wr_en_a_n, for one
clk_port_a_n
cycle. Internally, the data is written to the next location of
the FIFO and a write address pointer is incremented. The wr_full_n,
wr_empty_n
flags are updated immediately after a write cycle. The
wr_level_n is updated on the following clock.
Figure 6 shows the waveforms intitializing and writing to a FIFO. The
FIFO in this example has a depth of eight. Therefore, after eight words
have been written to the FIFO, wr_full_n goes high. Notice that
wr_full_n
also goes high for one clock cycle before the FIFO is full. If the
wr_full_n flag is high while the wr_level_n flag does not indicate the
FIFO is full, it means the FIFO is busy and cannot accept write operations.
Wait for the wr_full_n flag to go low before attempting to write another
word to the FIFO.
Figure 6. Initializing and Writing to a FIFO
FIFO Read-port Functionality
Each FIFO read-port includes an independent set of control and data
signals. The clk_port_b_n input is used to clock the read operations for
FIFO n. In the MegaWizard, the user specifies whether the read_b_n
signal should act as a read request or a read enable signal.
32 1 2 5 4 3 6 8 7 9 10
clk_port_a_0
32 1 2 5 4 3 6 7 0
aclr
tdm_clk
wr_en_a_0
wr_data_a_0
wr_level_0
wr_empty_0
wr_full_0