Simulating fifo partitioner functions – Altera First-In-First-Out Partitioner User Manual

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Altera Corporation

FIFO Partitioner Megafunction User Guide

Getting Started

1

Logic internal to the MegaWizard-generated function must
operate at the TDM clock frequency. Static timing analysis
within the MegaWizard-generated function on the individual
FIFO clock domains is not necessary. The FIFO Partitioner
function operates correctly if the specified frequencies for all
clocks are used and the TDM clock is operating within its
reported fmax limit.

Simulating FIFO Partitioner Functions

Standard simulation techniques are available for FIFO Partitioner. It is
necessary for third-party EDA simulation tools to synthesize the library
files listed above, and altera_mf_components model located in the
<quartus_directory>\eda\sim_lib directory, for third-party EDA synthesis
in order to simulate FIFO Partitioner functions correctly. Two hex files
output by the FIFO Partitioner MegaWizard, called
<function_name>_a.hex and <function_name>_b.hex must also be included
for successful third-party simulation.

To perform functional simulation in an third-party EDA tool without
VHDL support, first synthesize the design in Quartus, and use the
<function_name>.vo file output by the Quartus software in your EDA
simulation tool.

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