Altera First-In-First-Out Partitioner - Manual (Page 16)

14 Altera Corporation
FIFO Partitioner Megafunction User Guide Getting Started
Figure 8 shows the identical situation as Figure 7 , except for a FIFO with
read_b_n operating as a read acknowledge. Notice that in this mode data
is available on rd_data_b_n before read_b_n is asserted.
Latency Effects
on Full and
Empty Flags of
FIFOs The flags wr_full_n and rd_empty_n signal to the user when writing
to and reading from the FIFO is restricted. In addition to becoming
asserted when the FIFO is full or empty, these flags may become asserted
for one or two clock cycles while the sequencer circuitry is busy servicing
previous memory accesses. The user should never attempt to write to a
FIFO whose wr_full_n flag is asserted, or read from a FIFO whose
rd_empty_n
flag is asserted. Doing so results in unspecified behavior.
An internal buffer is used to make FIFO data available immediately to the
rd_data_b_n
. Because this internal buffer is smaller than the FIFO,
many successive read operations may cause rd_empty_n to be asserted
for one or two port clock cycles when the FIFO is not empty. When the
rd_empty_n
flag is asserted, the user is not allowed to assert the
read_b_n signal. To minimize the occurrences of rd_empty_n being
asserted when the FIFO is not empty, use the maximum possible
TDM_clk
frequency.
Similarly, when performing many successive write operations to the
FIFO, the wr_full_n flag may be asserted for one or two clock cycles
before the FIFO is full. Write operations to the FIFO while wr_full_n is
asserted are prohibited. To minimize the occurrences of wr_full_n
being asserted when the FIFO is not empty, use the maximum possible
TDM_clk
frequency.
Mixed-width
FIFOs The FIFO Partitioner supports mixed-width FIFO functions. This section
describes the behavior of mixed-width FIFOs. The following examples use
FIFOs with read_b_n operating as a read request signal.
FIFOs with a wide write port and a narrow read port
Figure 9 illustrates write and read operations to a FIFO with a 16-bit-wide
write-side bus, and a 8-bit-wide read-side bus. In this example the read
port is operating at twice the frequency of the write port. Two 16-bit
words are written to the FIFO. Notice that the wr_level_2 flag is
incremented to 2, and the rd_level_2 flag is incremented to 4. Four 8-bit
word read operations empty the FIFO. Notice that the least-significant 8
bits from the 16-bit word written are read first, followed by the
most-significant 8 bits.