Altera First-In-First-Out Partitioner - Manual (Page 21)

Altera Corporation 19
Getting Started FIFO Partitioner Megafunction User Guide
Using Third-Party EDA Tools for Synthesis
When using third-party EDA tools for synthesis, it is recommended that
the FIFO Partitioner function be black-boxed. If you include only the
MegaWizard-generated file along with your design, supported EDA
synthesis tools automatically black-box the alt_csm_core instantiation
the Quartus software synthesizes it during pre-place-and-route synthesis.
To synthesize the alt_csm_core function in a third-party EDA
synthesis tool, the tool must support VHDL synthesis and your project
must include:
■ <function_name>.vhd or <function_name>.v
■ The ALTERA_MF_COMPONENTS.VHD file located in the
<quartus_directory>\libraries\vhdl\altera_mf directory
■ The following library files located in the
<quartus directory>\libraries\megafunctions directory:
–
alt_csm_unidpram_wr.vhd
– alt_csm_rom_wrapper.vhd
– alt_csm_fifo.vhd
– alt_csm_mux_rd.vhd
– alt_csm_mux_wr.vhd
– alt_csm_rom_wrapper.vhd
– alt_csm_sequence.vhd
– alt_csm_unidpram_com_bus_rd.vhd
– alt_csm_unidpram_com_bus_wr.vhd
– alt_csm_core.vhd
1 The wizard-generated file must be analyzed by third-party
synthesis tools before alt_csm_core because it defines a
package which is used in alt_csm_core.
Static Timing Analysis for FIFO Partitioner Functions
By default, the Quartus II software automatically performs static timing
analysis after placement and routing. You should specify an f
max
timing
requirement for the TDM_clk that is equal to or greater than the value
specified in the MegaWizard output info file. After compilation, verify
that the reported fmax for TDM_clk is greater than the intended operating
frequency for TDM_clk. Optimize the design, or reconfigure your FIFO
Partitioner function if necessary.