Altera PowerPlay Early Power Estimator - Manual (Page 19)

Altera Corporation 3–3
October 2005 PowerPlay Early Power Estimator User Guide: Stratix, Stratix GX & Cyclone FPGAs
Using PowerPlay Early Power Estimator for Stratix, Stratix GX & Cyclone FPGAs
The Stratix and Stratix GX PowerPlay early power estimator reflect the
actual clock resources in the device by providing 16 rows for the global
clock network, 16 rows for the regional clock network, and 8 rows for the
fast regional clock network.
1
Cyclone devices have eight global clock networks. They do not
have regional clock or fast regional clock networks.
Each row in the Clock Network section represents a clock network or a
separate clock domain. For each clock network used, you need to enter
the clock frequency (f
MAX
) in MHz and the number of flip-flops fed by the
clock. Table 3–1 describes the values that are entered in the Clock
Network section of the PowerPlay early power estimator.
Table 3–1. Clock Network Section Information (Part 1 of 2)
Column Heading Description
Clock Network Enter a name for the clock network in this column. This is an optional value.
f
M A X
(MHz) Enter the clock frequency for the clock network. This value is limited by the maximum
frequency specification for the device family.
# Flip-Flops Enter the number of registers driven by the clock network. The number of flip-flops driven
by every global clock, regional clock, and fast regional clock signal is reported in the Fan-
out column of the Quartus II Compilation Report under Fitter > Resource Section >
Global & Other Fast Signals > Fan-out. This value is limited by the number of logic
elements (LEs) available in the largest device in the family. You should verify that the
number of flip-flops entered does not exceed the number of LEs available in your target
device because the PowerPlay early power estimator does not verify this.
# DSP Blocks Enter the number of DSP blocks driven by the clock network. The number of DSP blocks
driven by every global clock, regional clock, and fast regional clock signal is reported in the
Fan-out column of the Quartus II Compilation Report under Fitter > Resource Section >
Global & Other Fast Signals > Fan-out.
(1)
# M512 Blocks Enter the number of M512 blocks driven by the clock network. The number of M512 blocks
is driven by every global clock, regional clock, and fast regional clock signal is reported in
the Fan-out column of the Quartus II Compilation Report under Fitter > Resource Section
> Global & Other Fast Signals > Fan-out.
(1)
# M4K Blocks Enter the number of M4K blocks driven by the clock network. The number of M4K blocks is
driven by every global clock, regional clock, and fast regional clock signal is reported in the
Fan-out column of the Quartus II Compilation Report under Fitter > Resource Section >
Global & Other Fast Signals > Fan-out.
(1)
MRAM Blocks Enter the number of MRAM blocks driven by the clock network. The number of MRAM
blocks is driven by every global clock, regional clock, and fast regional clock signal is
reported in the Fan-out column of the Quartus II Compilation Report under Fitter >
Resource Section > Global & Other Fast Signals > Fan-out.
(1)
I
C C I N T
(mA) This shows the estimated I
C C I N T
, in mA, based on the f
M A X
and number of flip-flops you
entered. This value is estimated automatically.