Ram blocks, Figure 3–10, Shows – Altera PowerPlay Early Power Estimator User Manual
Page 27: Figure 3–11
Advertising
Altera Corporation
3–11
October 2005
PowerPlay Early Power Estimator User Guide: Stratix, Stratix GX & Cyclone FPGAs
Using PowerPlay Early Power Estimator for Stratix, Stratix GX & Cyclone FPGAs
Figure 3–10. Phase-Locked Loops (PLLs) Usage in Compilation Report
Figure 3–11. Phase-Locked Loops (PLLs) Section in the Stratix PowerPlay Early Power Estimator
RAM Blocks
Stratix and Stratix GX device TriMatrix
™
memory consists of three types
of RAM blocks:
■
M512 blocks
Advertising