Altera PowerPlay Early Power Estimator - Manual (Page 30)

3–12 Altera Corporation
PowerPlay Early Power Estimator For Stratix II, Stratix II GX & HardCopy II January 2007
PowerPlay Early Power Estimator Inputs
RAM Mode Select from the following modes:
● Single-Port
● Simple Dual-Port
● True Dual-Port
● ROM
The mode is based on how the Quartus II Compiler implements the RAM. If you are
unsure how your memory module is implemented, Altera recommends compiling a
test case in the required configuration in the Quartus II software. The RAM mode
can be found in the Mode column of the Quartus II Compilation Report.
In the Compilation Report, select Fitter, and click Resource Section. Click RAM
Summary.
A single-port RAM has one port with a R/W control signal. A simple dual-port RAM
has one read port and one write port. A true dual-port RAM has two ports, each with
a R/W control signal. ROMs are read-only single-port RAMs.
Port A – Clock Freq Enter the clock frequency for port A of the RAM block(s) in MHz. This value is
limited by the maximum frequency specification for the RAM type and device
family.
Port A – Enable % Enter the average percentage of time the input clock enable for port A is active,
regardless of activity on RAM data and address inputs. The enable percentage
ranges from 0 to 100%. The default is set to 25%.
RAM power is primarily consumed when a clock event occurs. Using a clock enable
signal to disable a port when no read or write operation is occurring can result in
significant power savings.
Port A – Write % Enter the average percentage of time port A of the RAM block is in write mode
versus read mode. For simple dual-port (1R/1W) RAMs, the write port (A) is
inactive when not executing a write. For single-port and true dual-port RAMs, port
A reads when not written to. This field is ignored for RAMs in ROM mode.
This value must be a percentage number between 0% and 100%. The default is
50%.
Port B – Clock Freq Enter the clock frequency for port B of the RAM block(s) in MHz. This value is
limited by the maximum frequency specification for the RAM type and device
family. Port B is ignored for RAM blocks in ROM or single-port mode.
Port B – Enable % Enter the average percentage of time the input clock enable for port B is active,
regardless of activity on RAM data and address inputs. The enable percentage
ranges from 0 to 100%. The default is set to 25%. Port B is ignored for RAM blocks
in ROM or single-port mode.
RAM power is primarily consumed when a clock event occurs. Using a clock enable
signal to disable a port when no read or write operation is occurring can result in
significant power savings.
Table 3–3. RAM Section Information (Part 2 of 3)
Column Heading Description