Altera PowerPlay Early Power Estimator - Manual (Page 64)

3–46 Altera Corporation
PowerPlay Early Power Estimator For Stratix II, Stratix II GX & HardCopy II January 2007
Power Analysis
■ Toggle rate for Decoder module
■ Toggle rate for RAM
■ Toggle rate for Filter
■ Toggle rate for Modulator
■ Toggle rate for Encoder
These estimates can be done in many ways. If similar modules were used
in the past with data inputs of roughly the same toggle rate, that
information can be leveraged. If there are MATLAB simulations available
for some blocks toggle rate information can be obtained. If the HDL is
available for some of the modules they can be simulated.
If the HDL is complete, the best way to determine toggle rate is to
simulate the design. The accuracy of toggle rate estimates depends
heavily on the accuracy of the input vectors. Therefore, determining
whether or not the simulation coverage is high gives you a good estimate
of how accurate the toggle rate information is.
The Quartus II software can determine toggle rates of each resource used
in the design if information from simulation tools is provided. Designs
can be simulated in many different tools and information provided for
the Quartus II software through a Signal Activity File (SAF). The Quartus
II PowerPlay Power Analyzer provides the most accurate power
estimate. The CSV output file from Quartus II can be used with the
PowerPlay Early Power Estimator spreadsheet for estimating power after
the design.
Airflow
The PowerPlay Early Power Estimator spreadsheet allows the designer to
specify the airflow present at the device. This value affects thermal
analysis and bears directly on the power consumed by the device. To
obtain an accurate estimate it is imperative to correctly determine the
airflow at the FPGA, not the output of the fan providing the airflow.
Often it is difficult to place the device adjacent to the fan providing the
airflow. As such, the path of the airflow is likely to traverse a length on
the board before reaching the device, thus diminishing the actual airflow
the device sees. In the example shown in
Figure 3–33 , a fan is placed at the
end of the board. The airflow at the FPGA is weaker than what it is at the
fan.