Altera Transceiver Signal Integrity - Manual (Page 28)

6–4 Chapter 6: Board Test System
Using the Board Test System
Transceiver Signal Integrity Development Kit, February 2013 Altera Corporation
Stratix V GT Edition User Guide
Board Information
The Board information control displays static information about your board.
■ Board Name —Indicates the official name of the board, given by the Board Test
System.
■ Board P/N —Indicates the part number of the board.
■ Serial number —Indicates the serial number of the board.
■ Factory test version —Indicates the version of the Board Test System currently
running on the board.
■ MAX II ver —Indicates the version of MAX II code currently running on the board.
The MAX II code resides in the
<install dir>\kits\stratixVGT_5sgtea7_si\examples directory. Newer revisions of
this code might be available on the
Transceiver Signal Integrity Development Kit,
Stratix V GT Edition page of the Altera website.
■ MAC —Indicates the MAC address of the board.
MAX II Registers
The MAX II registers control allow you to view and change the current MAX II
register values as described in
Table 6–1 . Changes to the register values with the GUI
take effect immediately.
■ SRST —Resets the system and reloads the FPGA with a design from flash memory
based on the other MAX II register values. Refer to Table 6–1 for more information.
■ PSO —Sets the MAX II PSO register. The following options are available:
■ Use PSR —Allows the PSR to determine the page of flash memory to use for
FPGA reconfiguration.
■ Use PSS —Allows the PSS to determine the page of flash memory to use for
FPGA reconfiguration.
Table 6–1. MAX II Registers
Register Name
Read/Write
Capability
Description
System Reset
(SRST)
Write only Set to 0 to initiate an FPGA reconfiguration.
Page Select Override
(PSO)
Read / Write
When set to 0, the value in PSR determines the page of
flash memory to use for FPGA reconfiguration. When set to
1, the value in PSS determines the page of flash memory to
use for FPGA reconfiguration.
Page Select Switch
(PSS)
Read only
Holds the current value of jumper J28 PGMSEL:
1 = user image
2 = factory image.
Page Select Register
(PSR)
Read / Write
Determines which of the up to eight (0-7) pages of flash
memory to use for FPGA reconfiguration. The flash memory
ships with pages 0 and 1 preconfigured.