Altera Transceiver Signal Integrity - Manual (Page 47)

Chapter 6: Board Test System 6–23
Configuring the FPGA Using the Quartus II Programmer
February 2013 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix V GT Edition User Guide
Target Frequency
The Target frequency control allows you to specify the frequency of the clock. The
Target frequency
control works in conjunction with the Set New Frequency control
button.
Clear
This control sets the Si570 programmable oscillator to a default frequency of 100 MHz.
The default frequency is unique to each oscillator.
f For all four default oscillator frequencies, refer to “Board Overview” in the Transceiver
Signal Integrity Development Kit, Stratix V GT Edition Reference Manual .
Set New Frequency
The Set New Frequency control sets the Si570 programmable oscillator frequency to
the value in the Target frequency control. Frequency changes might take several
milliseconds to take effect. Altera recommends resetting the FPGA logic after
changing frequencies.
1 When a frequency change is made, the oscillator will always change back to its default
value first and then to the programmed value.
Configuring the FPGA Using the Quartus II Programmer
You can use the Quartus II Programmer to configure the FPGA with a .sof. Before
configuring the FPGA, ensure that the Quartus II Programmer and the USB-Blaster
driver are installed on the host computer, the USB cable is connected to the
development board, power to the board is on, and no other applications that use the
JTAG chain are running.
1 If you connect an external USB-Blaster download cable and power cycle the board, the
on-board Blaster is disconnected and the S5_UNLOCK function (
Table 4–4 on
page 4–4 ) does not allow JTAG access to the FPGA. To successfully use the
USB-Blaster cable, disconnect it before power cycling the board. After you power
cycled the board, then reconnect the USB-Blaster cable.
To configure the Stratix V GT FPGA, perform the following steps:
1. Start the Quartus II Programmer.
2. Click Auto Detect to display the devices in the JTAG chain.
3. Click Add File and select the path to the desired .sof.
4. Turn on the Program/Configure option for the added file.
5. Click Start to download the selected file to the FPGA. Configuration is complete
when the progress bar reaches 100%.
1 Using the Quartus II programmer to configure a device on the board causes other
JTAG-based applications such as the Board Test System and the Power Monitor to lose
their connection to the board. Restart those applications after configuration is
complete.