Sundance SMT130 v.1.0 - Manual (Page 16)

Page 16 of 46 SMT130 User Manual V1.0
8 Comport to PCI Interface
The Comport interface is memory mapped to the PCI Bridge as illustrated in table 2 :
I/O address space map. The Comport uses the Control and Data registers to detect
the state of the input and output FIFO. The following section describes the bit
definitions for these registers.
8.1 Comport Registers (Offset 0x10, BAR1)
The host is connected to the first TIM site using Comport 3. This port is bi-directional
and will automatically switch direction to meet a request from either the host or the
DSP. Both input and output registers are 32 bits wide. Data can only be written to
COMPORT_OUT when STATUS[OBF] is 0. Data received from the DSP is stored in
COMPORT_IN and STATUS[IBF] is set to 1. Reading COMPORT_IN will clear
STATUS[IBF] and allow another word to be received from the DSP.
8.2 Control Register (Offset 0x14, BAR1)
The CONTROL register can only be written. It contains flags, which control the boot
modes of the first TIM site.
7-5 4 3 2 1 0
notNMI IIOF2 IIOF1 IIOF0 RESET
RESET Write a 1 to this bit to assert the reset signal to the TIM
module on the SMT130.
IIOF0
IIOF1
IIOF2 These bits connect to the corresponding pins on the TIM site
1. Writing 0 causes the corresponding IIOF line to go low.
NotNMI A 0 written to this bit will assert the active low NMI to the
TIM.
Table 6 : Control Register
Note 1. On PCI system reset, RESET is asserted to the TIM site.
Note 2. The TIM reset signal on the STM130 is connected to a stacking connector
that can common up the TIM reset signals. If there is more than one SMT130 card in
a system stack, the TIM reset signal can be connected together if the reset enable
jumper is inserted. This maybe required where all TIMs in a system are to be reset at
the same time.