Sundance SMT130 v.1.0 - Manual (Page 31)

Page 31 of 46 SMT130 User Manual V1.0
full, the arbitration logic de-asserts the RDY1 signal to indicate a hold-off state. Once
the data has been transferred from the FIFO to the PCI bus RDY1 is re-asserted to
continue the transfer. The end of the burst access is indicated by asserting STAT0
low. If RDY1 is not active then STAT0 should remain asserted until ready is asserted
and the final data transaction has been completed.
Situations can arise where a deadlock condition car arrive, i.e. the PCI bus is trying to
read from the SMT130 resources while the DSP is reading from the PCI Bus. If this
situation arises the arbitration unit gives the PCI Bridge device priority and services
the HOST PCI access before giving bus ownership back to the DSP.
When running code composer applications to debug the DSP a reduction in the
speed of the debugger will be noticed. The DSP has priority when accessing the
local bus and any other accesses will only occur under the following conditions.
• Burst access is finished
• Deadlock condition occurs which releases DSP ownership of the Bus.
For multi-threaded applications the length of the DSP burst can be lowered to allow
PCI bus R/W cycles to snatch cycles from the DSP.