Sundance SMT130 v.1.0 - Manual (Page 37)

Page 37 of 46 SMT130 User Manual V1.0
1 DMA1 DMA channel 1 interrupt enable
0 DMA0 DMA channel 0 interrupt enable
Table 12 : Local Bus Interrupt Mask Register
13.3.4 Local Bus Interrupt Status Register(Offset 0x76, BAR0)
Bits Name Description
7 MAILBOX 1=interrupt has been requested by one or more of the
mailbox registers
0=no mailbox interrupts pending
6 PCI_RD See V3 datasheet
5 PCI_WR See V3 datasheet
4 PCI_INT See V3 datasheet
3 PCI_PERR See V3 datasheet
2 I2O_QWR See V3 datasheet
1 DMA1 See V3 datasheet
0 DMA0 See V3 datasheet
Table 13 : Local Bus Interrupt Status Register
13.3.5 PCI Mailbox WRITE/READ Interrupt Control Register(Offset: Write 0xD0,
BAR0 Read 0xD2, BAR0)
Bits Name Description
15 EN15 Local interrupts on PCI bus writes/reads to mailbox15
enable
14 EN14 Same as above for mailbox 14
13 EN13 Same as above for mailbox 13
12 EN12 Same as above for mailbox 12
11 EN11 Same as above for mailbox 11
10 EN10 Same as above for mailbox 10
9 EN9 Same as above for mailbox 9
8 EN8 Same as above for mailbox 8
7 EN7 Same as above for mailbox 7
6 EN6 Same as above for mailbox 6
5 EN5 Same as above for mailbox 5
4 EN4 Same as above for mailbox 4