Functional description, 2 functional description – Sundance SMT130 v.1.0 User Manual
Page 9
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
2 Functional
Description
The PCI interface connects to a Quick Logic EPC363 Bridge device. It has a 32-bit
33MHz PCI interface that supports I
2
C control, mailbox register access and direct
memory reads and writes. The PCI bus is translated to a Local PCI bus, which is
connected to the following devices:
• Shared SRAM 1MB
• Control EPLD that manages Comport access
• JTAG controller
• Module Global Bus
• PCI Bridge device
An on-board arbitration unit controls which device, Master Module or PCI Bridge, has
access to this local PCI bus resource.
The local PCI bus has a 33MHz clock to control transfers between the various
resources. This is available on the CLKIN pin on the Master site and should be
selected in preference to the on-board oscillator to allow the DSP to synchronise its
accesses to and from the PCI Bridge registers. The PCI Bridge has an input and
output FIFO capable of transferring 256 32-bit words of data to and from the DSP at
33MHz, thus bursting a maximum local bus transfer rate of 132MB/s.
The TIM Module can access the SRAM over the PCI local bus at transfer rates up to
100MB/s. The number of wait states required by the Master Module will vary
depending on the speed of the module. Maximum access rates use a 20ns strobe
cycle.
The JTAG controller is based on the TI 8990 device, and drivers can be supplied for
Code Com