Sundance SMT130 v.1.0 - Manual (Page 26)

Page 26 of 46 SMT130 User Manual V1.0
The mailbox registers are accessed from the DSP through the Local-to-Internal
Register (LB_IO_BASE) aperture. As illustrated in section 5, table 4 of this document
this region is accessed by the DSP via a global bus access to the PCI Bridge
Registers (Address : 0x1C00 0000).
The mailbox registers themselves are on byte boundaries with offsets 0xC0 -> 0xCF,
from the LB_IO_BASE. As DSP global bus accesses are carried out on WORD (32-
bit) boundaries a write access over the global bus to 0x1C00 0000 + 0xC0 will write
to the first 4 mailbox registers in the PCI Bridge device.
The mailbox registers are accessed from the PCI bus through the PCI-to-Internal
Register (PCI_IO_BASE) aperture. This is accessed via the PCI Bridge Chip Internal
Register (BAR0), byte offset 0xC0 -> 0xCF.
12.1.1 Doorbell Interrupts
Each of the 16 mailbox registers can generate four different interrupt requests called
doorbell interrupts. Each of these requests can be independently masked for each
mailbox register. The four doorbell interrupt types are:
• DSP interrupt request on read from PCI side
• DSP interrupt request on write from PCI side
• PCI interrupt request on read from DSP side
• PCI interrupt request on write from DSP side
The PCI read and DSP read interrupts are OR’d together and latched in the mailbox
read interrupt status register (MAIL_RD_STAT). Similarly, the PCI write and DSP
write interrupts are OR’d together and latched in the mailbox write interrupt status
register (MAIL_WR_STAT). All of the interrupt request outputs from the status
registers are OR’d together to form a single mailbox unit interrupt request and routed
to both the Local and PCI Interrupt Control Units.
When a block of mailbox registers are accessed simultaneously, for example when 4
mailbox registers are read as a word quantity, then each register affected will request
a separate interrupt if programmed to do so.
See section 14 for further information on Interrupts.
12.2 DSP Interrupt Control
Interrupts can be enabled from a number of different sources i.e. DSP-> Host and
Host -> DSP. See section 14 for a description of these functions.