Sundance SMT370v2 - Manual (Page 11)

Version 2.0 Page 11 of 46 SMT370v2/v3 User Manual
ADCs and DAC.
The SMT370 is populated with two AD6645s (2 channels) and one AD9777 (dual
channel). For more details about these converters (inner characteristics), please refer
to the manufacturer (Analog Devices) datasheets.
Data and control lines of the converters are all connected to the FPGA.
Clock management.
The SMT370 has two identical on-board low-jitter clock synthesizers ( ICS8430 ), one
for the ADCs and one for the DAC. Both have a Serial Port Interface. The FPGA is
responsible for setting them to the correct values loaded into a control register. A
wide range of frequencies can be set this way. The SPIs are write-only, i.e. they can’t
be read back directly from the chip.
Clock multiplexers are also available on the board to route the appropriate clock
signal (from external or on-board source) to the converters. It is usual to have both
ADCs fed with the same sampling clock but it is possible to have an ADC receiving
the external clock and the second one receiving the on-board clock. In this particular
case, two 16-bit interfaces are necessary to transfer samples to an external TIM. The
DAC is fed either with an on-board/DAC or external clock coming from connector
J14. The clock selection is made via the control register.
Sundance High-speed Bus - SHB.
The SMT370 provides 2 full SHB (Sundance High-speed Bus) connectors, labelled
SHBA (J3) and SHBB (J4) – see Figure 13 - Connector Location.)
SHBA is set as transmitter only to transfer data coming from the Analogue-to-Digital
Converters to an external SHB module, for instance SMT365, SMT365E or SMT374.
SHBB is set as a receiver only and is dedicated to receive data for the Digital-to-
Analogue converter. Transfers at up to 100 MHz are supported on these two SHB
connectors.
SHBA – ADCs.
The FPGA routes the data lines coming from the ADCs to SHBA. Data lines go
through 7 latch stages inside the FPGA, which means that it takes 7 sampling clock
cycles for a sample to go from the ADC to SHBA. The board offers to possibility to
output data in either two’s complement or binary format. It is also possible to output a
16-bit counter on each SHB half for system testing purpose – It then becomes easier
to detect any missing data. ADCA is mapped onto the lowest part of SHBA and
ADCB onto the highest.
As the SMT370 is populated with two ADCs, two data stream are theoretically
available on SHBA. Each of them can be synchronised to either an external sampling
clock or an on-board clock. In the FPGA, each data stream goes through a
Decimator, which value (0 to 31) can be set via control register. Both decimators are
independent. If both decimators are set with the same values and if the sampling
clocks (for Channel A and Channel B) are the same, i.e. both ADCs are using either
the external or the on-board clock, both data streams are synchronised with each