Sundance SMT370v2 - Manual (Page 13)

Version 2.0 Page 13 of 46 SMT370v2/v3 User Manual
1 -> Flashing under the ADC sampling clock (it can be useful to check that the
LED is flashing when using an external sampling clock signal),
2 -> Flashing under the DAC sampling clock,
3 -> Direct To DAC mode selected when ON,
4 -> ON when a data is being read out of the DAC FIFO.
Two green LEDs, located at the bottom left and right of the board indicate the status
of the power supplies. Both should be on when the board is under power.
A red LED located on the top right of the board indicated when the FPGA is not
programme. In normal operation, i.e. J8 fitted (Figure 13 - Connector Location.), it
flashes once at power-up and after resetting the module.
Just after a reset (TIM or FPGA Global Reset), the LEDs display the Firmware
version. This is available from the Version 4 of the Firmware. For earlier version, the
LEDs are connected to un-driven signals:
LED1=ON, LED2=OFF, LED3=ON and LED4-OFF => Version 2.5 of the firmware
LED1=OFF, LED2=ON, LED3=ON and LED4-OFF => Version 3.6 of the firmware
TTL I/Os.
Four TTL I/Os (J6 – see Figure 13 - Connector Location.) are connected directly to
the FPGA. They support LVTTL signals. It is recommended to make sure the lines
connected to these pins are LVTTL compatible in order not to damage the FPGA
pads, as lines are not clamped.
Sundance Standards.
Communication Ports (ComPorts).
According to the Sundance module you can get up to six 8-bit, data-parallel, inter-
processor links that follow Texas Instruments’ TMS320C4x Communication Port
standard. Additional information on the standard is available in the TMS320C4x
User’s Guide chapter 12:
Communication ports and the Texas Instrument Module
Specification .
The standard gives a TIM six links numbered from 0 to 5. Each link can be a
transmitter or a receiver, and will switch automatically between these states
depending on the way you use it. Writing to a receiver or reading from a transmitter
will cause a hardware negotiation (token exchange) that will reverse the state of both
ends of the link.
Following a processor reset, the first three links (0, 1, and 2) initialise as transmitters
and the remainder (3, 4, and 5) initialise as receivers. When you wire TIMs together