Sundance SMT370v2 - Manual (Page 41)

Version 2.0 Page 41 of 46 SMT370v2/v3 User Manual
SHBB works either on 16 or 32 bits (see also
SDB_technical_specification_v_2_1.pdf ):
- 16 bits: each half of SHBB is 16-bit wide and has its own set of control signals
(Clock, Write enable and acknowledge). When Channel A and Channel B are
enabled (Bit24 and Bit25 set to ‘1’), both FIFOs ‘wait’ for each other to read
out data to make sure that samples on both DAC ports (P1B and P2B) carry
synchronised samples.
- 32 bits: if both sets of control lines are driven by the same signals, SHBB
becomes 32-bit compatible and each 32-bit data carries two synchronised
samples.
Channel Enable B
Channel Enable A
DAC Sampling Clock
J12
DAC
Port P1B
(I)
16-bit data
FIFO
2048 words
16-bit data
Write Enable1
SHB Clock1
Acknowledge1
J13
DAC
Port P2B
(Q)
16-bit data
FIFO
2048 words
16-bit data
Write Enable0
SHB Clock0
Acknowledge0
S
H
B
B
C
O
N
N
E
C
T
O
R
Figure 15 - SHBB data path.