Sundance SMT370v2 - Manual (Page 36)

Version 2.0 Page 36 of 46 SMT370v2/v3 User Manual
F
Synthesized
= (M/N) MHz - With 500 < M < 250 (binary encoding) and N can take one of
the following values: 1 (“000”), 1.5 (“001”), 2 (“010”), 3 (“011”), 4 (“100”), 6 (“101”), 8
(“110”) or 12 (“111”). See
ICS8430-01 datasheet for more information performance,
jitter, etc.
The following diagram shows how clock signals can be routed on the PCB.
A and B
Xilinx
FPGA
Virtex-II, FG456
XC2V1000-6
324 I/O Pins
1.5V Core
3.3V I/O
#1
AC or DC
coupling
2xAD6645 ADCs
14-bit @ 105MSPS
52-pin LQFP
30 I/O pins; 28-bit data; ctl
1x AD9777 DAC
16-bit @ 400MSPS
80-pin TQFP
44 I/O pins; 16-bit data; ctl
#4 #3
RF
transformer
#2
Clock feedbacks
Clock feedback
Clk
1 opamp
opamp
Clock synthe-
sizer ADCs
Clk
2
AC or DC
coupling
RF
transformer
ADC A ADC B
Clock synthe-
sizer DAC
Bit27
0
1
Bit26
0
1
0
1
0
1
Bit25 Bit24
Figure 14 - Clock Routing.
The skew between ADC clock signals is negligible, which means that samples
coming from both converters can be considered as synchronised when Bit26 and
Bit27 are the same.
It is to the user not to set too high frequencies, i.e. higher than 105MHz for the ADCs
and 160MHz for the DAC. This could damage the converters.