Sundance SMT370v2 - Manual (Page 12)

Version 2.0 Page 12 of 46 SMT370v2/v3 User Manual
other and therefore the two 16-bit data streams can be considered as a single 32-bit
data stream.
It is possible to control (start/stop) the data flow by the way of an external trigger, for
which the active level (high or low) can be set in a control register. It is recommended
to have external trigger signal synchronised to the sampling clock. This external
trigger also goes thought 7 latch stages.
SHBB – DAC.
Data received on SHBB are samples routed to the DAC. Data from both SHBB
channels go through a first row of latched, then stored into a FIFO, read out and
finally go through two rows of latches. It takes at least 4 DAC sampling clock cycles
to go through the FPGA. As both channels of the DAC are not necessarily
synchronised, the two FIFOs are read out at the same time as soon as there is a
least one data in each FIFO – it is the case when using two independent 16-bit
interfaces. To avoid synchronisation problems, SHBB can be used as a single 32-bit
interface. Simply drive both sets of control register with the same signals. DAC-
Channel A is mapped onto the lowest part of SHBB and DAC-Channel B onto the
highest.
Communication Ports (ComPorts).
The SMT370 provides 2 physical ComPorts: 0 and 3. The default bit stream provided
implements ComPort 3 (Input at reset) to load control registers. A physical
connection to a ComPort 0, 1 or 2 (Output at reset) is therefore necessary, to an
SMT365 for instance. Please report to the part dealing with ComPorts
(Communication Ports (ComPorts).) in this document for more details.
External triggering.
Two external trigger connectors (J15 and J16 – see Figure 13 - Connector Location.)
are available on the board to start or stop converters from an external source. The
selection is made via a control register, where channel selection can also be set.
Triggering consists in enabling or disabling the converters (ADCs and/or DAC). This
is available and accurate as long as the triggering signals are synchronised on the
sampling clock. Trigger signals can be set as active high or low in via the control
register.
Each trigger input is clamped to 3.3 and Ground to avoid damaging the FPGA I/Os.
This is achieved by using single diodes (
BAV99 ). These diodes can support as
maximum, 200mA of forward current and 70 Volts of reverse voltage. It is to the
customer to consider this when building a system using an SMT370.
LEDs.
Seven LEDs (Figure 13 - Connector Location.) are available on the board. Four
(denoted 1, 2, 3 and 4 on the PCB – top left) of them, green, are driven by the FPGA.
In the default bitstream, they indicate what follows: