Sundance SMT329 - Manual (Page 20)

4.2.3 CPLD
The CPLD performs 3 primary functions: It loads the fpga configurations and comms port
switch map from flash, immediately after power on. It also manages the JTAG switching
required to maintain an intact serial data stream with any number of TIM slots occupied. It
also controls the low level board reset.
The flash is divided into a user area and a factory area. An SMT329 is shipped with both
these areas containing a Spartan 3 configuration, a standard comms port map, and a Virtex 4
configuration. The user can choose which area is used by the CPLD to load from, by setting
DIP switch SW2 bit 4 as follows:
SW2/4 OFF = Factory area (UVB4 = 1)
SW2/4 ON = User area (UVB4 = 0)
If the CPLD fails to configure an FPGA using the user area data, it will then try loading from
the factory area.
User Manual SMT329 Page 20 of 52 Last Edited: 09/02/2007 10:58:00