Sundance SMT329 - Manual (Page 32)

and then the lower data bits to address
IO base + 0x86-0x87.
This register, when read, contains the next 32 bit word received from the comm port. Writing
to this register causes a 32 bit word to be sent to the comm port. The receive and transmit
sections of this register are separate and each includes a 512 deep by 32 bit wide fifo.
The SMT329 implements 2 separate comms port channels between the Virtex4 and the
Spartan3 comms port switch. These channels are multiplexed inside the Virtex4 so that either
one may be active at any given moment. Independent hand shake control is provided for each
channel, although there is only 1 receive fifo and 1 transmit fifo. This means that channel
switching can be done at any time, with no loss of data. Transfers simply halt on the disabled
comms port, and remain frozen until that comms port is enabled.
4.5.1.2 Comm Port Status1 register
The status1 register is accessible by the VME host at address
IO base + 0x90-0x93. The bit definitions for this register are:
31 30 29 28 27 26 25 24
Token1 Idle1 Token2 Idle2 Rxalemp Rxalfull Rxemp Rxfull
R, 1 R, 0 R, 1 R, 0 R, 1 R, 0 R, 1 R, 0
23 22 21 20 19 18 17 16
Rxrderr Rxwrerr Txalemp Txalfull Txemp Txfull Txrderr Txwrerr
R, 1 R, 0 R, 1 R, 0 R, 1 R, 0 R, 1 R, 0
15 14 13 12 11 10 9 8
-Txfull -Rxemp -Txfull -Rxemp
R, 0 R, 0 R, 0 R, 0 R, 1 R, 0 R, 1 R, 0
7 6 5 4 3 2 1 0
R, 0 R, 0 R, 0 R, 0 R, 0 R, 0 R, 0 R, 0
Bit Mnemonic Description
Token1 Comms port VXC1 has the transmit token
Idle1 Comms port VXC1 is idle
Token2 Comms port VXC2 has the transmit token
Idle2 Comms port VXC2 is idle
Rxalemp Receive fifo almost empty (has 128 entries left)
User Manual SMT329 Page 32 of 52 Last Edited: 09/02/2007 10:58:00